This invention relates to a decode circuit for decoding an input signal into an output signal. It is noted throughout the instant specification that the input signal may be considered as a frame synchronization signal which is followed by a data signal, although this invention is not restricted to decoding the frame synchronization signal.
A decode circuit of the type described decodes frame synchronization signal in synchronism with a clock signal into a decoded signal or an intermediate signal having a variable pattern. When the variable pattern of the intermediate signal is identical with a predetermined pattern, the decode circuit outputs the intermediate signal as an output signal.
In order to obtain the output signal, it is necessary to vary the clock signal into a varied clock signal which has a phase different from a phase of the clock signal in accordance with the intermediate signal. Namely, such a varied clock signal must be traced with time to correctly obtain the output signal.
Inasmuch as the varied clock signal must be traced with time, the decode circuit is disadvantageous in that the amount of hardware required increases.